1. Field of the Invention
The present invention relates to a pixel unit, a liquid crystal display (LCD) panel, and method for forming the same, and more particularly, to a pixel unit, an LCD panel, and method for forming the same for improving the problem of uneven display brightness due to a G/D overlay tolerance between a gate electrode (GE) layer and a source/drain electrode (SD) layer.
2. Description of Prior Art
A monitor with multiple functions is a key element for use in current consumer electronic products. The demand for the novelty and colorful monitors with high resolution, e.g., liquid crystal displays (LCDs), are indispensable components used in various electronic products such as monitors for notebook computers, personal digital assistants (PDAs), digital cameras, and projectors.
While the size of an LCD panel becomes larger, a mura phenomenon due to uneven brightness in a panel occurs more frequently than ever. Currently two main types of forming processes for LCD panels exist: a four-mask process and a five-mask process. The four-mask process has gradually become the mainstream owing to its short production cycle time and high rates of capacity utilization. However, the four-mask process is more complicated in alignment than the five-mask process, so it is more difficult to achieve high standards of production yields now for the four-mask process.
Currently, an LCD panel formed by using a four-mask process undergoes the following steps: At First, a metallic layer on a glass substrate is exposed and etched through a first mask to form a gate electrode (GE) layer of a switch unit. Next, an isolation layer and an active layer are formed on the GE layer. Subsequently, another metallic layer is deposited on the isolation layer and the active layer. At last, the metallic layer is exposed and etched through a second mask to form a source/drain electrode (SD) layer of the switch unit and a data line. Nowadays, the industry primarily utilizes a mask aligner to adopt a so-called mix-and-match approach to enhance capacity utilization. That is to say, while the GE layer and the SD layer are being formed, the metallic layers are exposed by different mask aligners, respectively. But, due to different processes in the utilization of different mask aligners, a tolerance in a G/D overlay between the GE layer and the SD layer tends to occur, causing a local shift in patterns to happen more frequently.
Please refer to FIGS. 1 through 3. FIG. 1 and FIG. 2 illustrate schematic diagrams of a shift of formed data lines relatively to pixel electrodes. FIG. 3 is an equivalent circuit diagram of a combination of FIG. 1 and FIG. 2. For the pixel electrodes 14a and 14b disposed on the same scan line 11, as shown in FIG. 1, the distance between the data line 12b and the pixel electrode 14b appears left shifted compared with the distance between the data line 12a and the pixel electrode 14a. So a coupling capacitor Cpd2 between the data line 12b and the pixel electrode 14b is larger than a coupling capacitor Cpd1 between the data line 12a and the pixel electrode 14a, as shown in FIG. 3. Although a data voltage which the data line 12a feeds into the pixel electrode 14a is consistent with a data voltage which the data line 12b feeds into the pixel electrode 14b, a charging voltage of the pixel electrode 14b is smaller than a charging voltage of the pixel electrode 14a, practically, so that the deflection polarity of liquid crystals (LCs) between an LC capacitor Clc1 and an LC capacitor Clc2 is not consistent. Accordingly, a gray level of the pixel electrode 14b is brighter than a gray level of the pixel electrode 14a. Relatively, for pixel electrodes 14c and 14d disposed on the same scan line 11, as shown in FIG. 2, the distance between the data line 12d and the pixel electrode 14d appears right shifted compared with the distance between the data line 12c and the pixel electrode 14c. So a coupling capacitor Cpd4 between the data line 12d and the pixel electrode 14d is smaller than a coupling capacitor Cpd3 between the data line 12c and the pixel electrode 14c, as shown in FIG. 3. Although a data voltage which the data line 12c feeds into the pixel electrode 14c is consistent with a data voltage which the data line 12d feeds into the pixel electrode 14d, a charging voltage of the pixel electrode 14d is larger than a charging voltage of the pixel electrode 14c, practically, so that the deflection polarity of liquid crystals (LCs) between an LC capacitor Clc3 and an LC capacitor Clc4 is not consistent. Accordingly, a gray level of the pixel electrode 14d is darker than a gray level of the pixel electrode 14c. In other words, if the GE layer and the SD layer have a slight tolerance in a G/D overlay, a problem of uneven display brightness may occur in an LCD panel.
It is necessary to consider the following capacitors for each pixel capacitor Cpix: an LC capacitor Clc, a storage capacitor Cs between a pixel electrode 14 and a common line 16, a parasitic capacitor Cgs between a gate and a source of a switch unit, and a coupling capacitor Cpd between a data line and a pixel electrode 14. As described above, a G/D overlay tolerance tends to cause a coupling capacitor Cpd to change. Besides, each pixel capacitor Cpix is a sum of the LC capacitor Clc, the storage capacitor Cs, the parasitic capacitor Cgs, and the coupling capacitor Cpd (i.e., Cpix=Clc+Cs+Cgs+Cpd). So, the more a ratio Q of the coupling capacitor Cpd to the pixel capacitor Cpix is, the more uneven display brightness in an LCD panel caused by a G/D overlay tolerance tends to becomes. Therefore, the industry needs to put effort into improving the problem of uneven display brightness due to change in the coupling capacitor Cpd caused by a G/D overlay tolerance.